By Rajesh Garg
This booklet is stimulated through the demanding situations confronted in designing trustworthy integratedsystems utilizing glossy VLSI strategies. The trustworthy operation of built-in Circuits (ICs) has develop into more and more tricky to accomplish within the deep sub-micron (DSM) period. With constantly lowering machine function sizes, mixed with reduce offer voltages and better working frequencies, the noise immunity of VLSI circuits is lowering alarmingly. hence, VLSI circuits have gotten extra susceptible to noise results similar to crosstalk, strength offer adaptations and radiation-induced tender errors.
This publication describes the layout of resilient VLSI circuits. It provides algorithms to research the harmful results of radiation particle moves and processing diversifications at the electric habit of VLSI circuits, in addition to circuit layout thoughts to mitigate the effect of those problems.
- Describes the state-of-the-art within the parts of radiation tolerant circuit layout and technique edition tolerant circuit design;
- Presents analytical ways to check successfully the severity of electric results of radiation/process adaptations, in addition to recommendations to lessen the results as a result of those problems;
- Distills content material orientated towards nuclear engineers into modern algorithms and methods that may be understood simply and utilized by means of VLSI designers.
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Extra info for Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
T/. This is reasonable since ’ is usually 3–4 times of “ and therefore e t = “ approaches 0 much faster than the max ) will e t = ’ term. Thus the value of e t = “ around t3 (which is greater than Tseu be approximately equal to 0. 8) Now, the radiation-induced current after time t3 is modeled by a line, one of avg VDDCjVTP j VDD=2 whose end-points has a current value of IDS D 0:5 (IDS C IDS ) at a time value of t3 . The other end-point has its current value as 0 at time t . t/ from time t3 to infinity and the charge deposited by linearized radiation-induced current equation.
11. P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583– 602, 2003. 12. Q. Zhou and K. Mohanram, “Gate sizing to radiation harden combinational logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155–166, Jan. 2006. 13. D. Binder, C. Smith, and A. Holman, “Satellite anomalities from galactic cosmic rays,” IEEE Transactions on Nuclear Science, vol.
3. For all experimental results reported in this section, Q D 150 fC, ’ D 150 ps, and “ D 50 ps. Similar results were obtained for the other values of Q, ’ , and “ . The proposed model was applied to inverters of different sizes (with both possible input values) for determining the pulse width of the voltage glitch induced by a radiation particle strike. The circuit under consideration is similar to Fig. 1a, where INV1 is driving either 1 or 3 inverters of the same size, and a radiation particle 36 2 Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits strike occurs at the output node of INV1.
Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations by Rajesh Garg