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Full-duplex operation. • Software programmable for one of 32 different baud rates. • Software selectable word length (eight or nine bit words). • Separate transmitter and receiver enable bits. • Capable of being interrupt driven. • Four separate enable bits available for interrupt control. 2 SCI Receiver Features • Receiver wake-up function (idle or address bit). • Idle line detect. • Framing error detect. • Noise detect. • Overrun detect. • Receiver data register full flag. 3 SCI Transmitter Features • Transmit data register empty flag.

The normal EEPROM control bits in the PPROG register are used for this purpose. Programming follows the same procedure as programming a byte in the 512-byte EEPROM except the CONFIG register address is used. Erase also follows the same procedure as that used for the EEPROM except that only bulk erase can be used on the CONFIG register. When the CONFIG register is erased, the 512-byte EEPROM array is also erased. Be sure to check the Technical Summary for the particular MC68HC11 Family member you are using.

The CPOL bit can be thought of as simply inserting an inverter in series with the SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA = 0, the shift clock is the OR of SCK with SS. As soon as SS goes low the transaction begins and the first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may be thought of as a simple output enable control. Refer to Figure 6-1. Table 6-1 Serial Peripheral Rate Selection SPR1 SPR0 Internal Processor, Clock Divide By 0 0 2 0 1 4 1 0 16 1 1 32 SPR1 and SPR0—SPI Clock Rate Selects These two serial peripheral rate bits select one of four baud rates (Table 6-1) to be used as SCK if the device is a master; however, they have no effect in the slave mode.

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68HC11 Technical Docs

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